主要特性与技术指标

DDR3、DDR4、DDR5、LPDDR2、LPDDR3、LPDDR4 和 LPDDR5 分析

使用 “事务解码" 和 “流量概况" 视图快速引导流量

在低功耗数据传输的事务解码之后的是自刷新进入/退出、多用途命令（MPC）、DDR4 3DS（DRAM 裸片 3 维堆叠）、LPDDR5 组织模式、速度变化和模式寄存器

查看 MB 数据速率和总线利用率百分比的性能计算结果和图形，通过图形滚动刷新窗口观察刷新速率，查看页面打开/关闭事务关联以及每个读取或写入事务所发送的数据

显示地址映射，查看由于刷新之间激活次数太多有出现 Row Hammer 问题风险的地址

DDR3、DDR4、DDR5、LPDDR2、LPDDR3、LPDDR4 和 LPDDR5 一致性验证

使用后期处理一致性违规工具来测试在存储速度变化时的协议一致性违规

使用后期处理或实时处理工具来识别 DDR/2/3/4/5 或 LPDDR/2/3/4/5 状态机、协议一致性、协议级总线周期时序违规

使用实时一致性违规分析工具自动执行实时 DDR2/3/4/5 或 LPDDR2/3/4/5 协议一致性测量和迹线捕获，节省大量时间

后期处理工具和实时工具均提供增强的参数编辑界面，可以让您轻松地编辑 DDR2/3/4/5 或 LPDDR2/3/4/5 标准预置测试的参数

ONFi（开放式 NAND 闪存接口）分析工具

使用密集的 ONFi 分析 “时间线" 视图，快速在多个 ONFi 目标之间进行导航

使用 ONFi 事务的 “详细信息" 视图，将 ONFi 操作视为序列中的一组逻辑关联命令，从而节省时间

列出用于 DDR、DDR2、DDR3、DDR4、LPDDR、LPDDR2、LPDDR3 和 LPDDR4 的

解码 DDR、DDR2、DDR3、DDR4、LPDDR、LPDDR2、LPDDR3 和 LPDDR4 命令以及 MRS 命令

包括 DDR4 RDIMM 和 LRDIMM 的 MRS 解码选项

使用用于 DDR/2/3/4 和 LPDDR/2/3 的物理地址触发工具，快速完成物理地址触发设置

Main Characteristics and Technical Indicators

Analysis of DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4 and LPDDR5

Quickly boot traffic using Transaction Decoding and Traffic Profile views

After transaction decoding of low power data transmission, refresh entry/exit, multi-purpose commａnd (MPC), DDR4 3DS (DRAM bare 3-D stack), LPDDR5 organization mode, speed change and mode register are implemented.

View the performance calculation results and graphics of MB data rate and percentage of bus utilization, observe the refresh rate through the graphical scroll refresh window, view the page open/close transaction Association and the data sent by each read or write transaction.

Display address maps to see addresses at risk of Row Hammer problems due to too many activations between refreshes

Conformity Verification of DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4 and LPDDR5

Using post-processing consistency violation tools to test protocol consistency violations when storage speed changes

Use post-processing or real-time processing tools to identify DDR/2/3/4/5 or LPDDR/2/3/4/5 state machines, protocol consistency, protocol-level bus cycle timing violations

Using real-time consistency violation analysis tools to automatically perform real-time DDR2/3/4/5 or LPDDR2/3/4/5 protocol consistency measurement and trace capture saves a lot of time.

Both post-processing tools and real-time tools provide enhanced parameter editing interfaces that allow you to easily edit parameters for DDR2/3/4/5 or LPDDR2/3/4/5 standard preset tests.

ONFi (Open NAND Flash Interface) Analysis Tool

Use intensive ONFi analysis of "timeline" views to quickly navigate between multiple ONFi targets

Using the "Details" view of ONFi transactions, ONFi operations are treated as a set of logically related commands in a sequence, saving time

List decoders for DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3 and LPDDR4

Decoding DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3 and LPDDR4 commands and MRS commands

MRS decoding options including DDR4 RDIMM and LRDIMM

Using physical address triggering tools for DDR/2/3/4 and LPDDR/2/3, we can quickly complete the physical address triggering settings.